General Description:

Candidate should have demonstrated history of having led multiple development activities. The lead developer will be expected to work on detailed low level specification of the methodologies to be developed. He/She will then work on development themselves as well as lead and guide any staff developers working in the same domain. He/She will need to deliver development per the bottoms up schedule that He/She will specify. He/She should have good understanding of what it takes to develop well structured and easily maintainable software. He/she need to be highly proficient in perl/tcl themselves and also capable of spot checking work done by staff developers to ensure accuracy, completeness, and good coding style to ensure production quality development.

He/she should have good customer/communication skills for enabling successful deployment and support. It should be noted that the role requires flexible work schedule. The leads would be expected to attend regular evening calls. They may also be expected to travel to US for multiple weeks.

Job Code: MFL5

Work Experience Requirements

• This position is expected to be highly experienced (8-10 years). The experience can be in one or more of the following three areas (in order of preference): (i) EDA methodology/flow development (ii) EDA vendor AE (iii) Digital design engineer. He/she should have expert working knowledge of the design flow and relevant EDA tools (Cadence expertise preferred) in the domain
• Must understand IR drop, its analysis and ways of implementing/correcting power architecture to manage the drop. Experience with dynamic IR background is preferred
• Should have worked on IR drop analysis of production designs to enable good understanding of sound methodology and third party tools. Cadence EPS experience preferred
• Tools: Preferable to have work experience with Cadence tools, but experience with other tools too would be considered
• Scripting and software languages: Perl / Tcl / C++

Education Requirements: Bachelor/Master in EE or ECE or Computer Engineering

Please send your resume with job code in the subject line or contact us at following address:
Interra Systems
Kalyani Platina, No.24, Phase I, 2nd Floor, EPIP Zone, Whitefield,
Bangalore – 560066
Phone: +91 80 25130200
Fax: +91 80 25130220
Email: HRindia@interrasystems.com

General Description:

Candidate should be an E&C/EE/Computer Science graduate with prior experience of Virtual prototype module, verification. He/She should have good understanding of what it takes to develop well structured and easily maintainable software. He/she needs to be highly proficient in C, C++ and ensure accuracy, completeness, and good coding style to ensure production quality development. He/She should be good at fundamentals of processor architecture and good at programming skills.

Job Code: INVP1

Work Experience Requirements

• Minimum 3 years hands on experience on Virtual Prototype module development, verification
• Fundamental knowledge of processor architecture, peripheral interface, different bus architecture
• Good programming skills in System C, C, C++

• Exposure to mobile chipset / product will be added advantage with preference ARM cores
• Perl / Shell scripting
• Work experience on VAST tools and VC++ is a plus

• Self motivated, analytical, flexible with good communication and ability to learn new areas, languages etc.
• Excellent written and verbal communication skills
• The candidate must be confident, self-sufficient, learn quickly, and have strong problem solving skills

Education Requirements: Bachelor/Master in Computer Engineering or equivalent from reputed institutional organizations

Please send your resume with job code in the subject line or contact us at following address:
Interra Systems
Kalyani Platina, No.24, Phase I, 2nd Floor, EPIP Zone, Whitefield,
Bangalore – 560066
Phone: +91 80 25130200
Fax: +91 80 25130220
Email: HRindia@interrasystems.com

General Description:

The individual will be responsible for development and support of virtual prototype model development and verification of designs. The job requires candidates to work with customers on their projects either at our office or customer place. Candidate should have good communication skills, both verbal and oral. He/She should be a good team player.

Job Code: IMCVP1

Work Experience Requirements

• Proficiency in System C, embedded  C and C++ is must
• Minimum 3 years hands on experience on Virtual Prototype module development, verification
• Fundamental knowledge  of processor architecture, peripheral interface, different bus architecture
• Exposure to mobile chipset/product will be added advantage with preference ARM cores
• Work experience on VAST tools and VC++ is a plus
• Familiarity with Configuration management Systems, preferably Clearcase

Education Requirements: B.E/B.Tech or M.E/M. Tech in EE/CS from reputed institution

Please send your resume with job code in the subject line or contact us at following address:
Interra Systems
Kalyani Platina, No.24, Phase I, 2nd Floor, EPIP Zone, Whitefield,
Bangalore – 560066
Phone: +91 80 25130200
Fax: +91 80 25130220
Email: HRindia@interrasystems.com

General Description:

The individual will be responsible and should lead/guide the verification team on new verification initiatives and technical guidance. The job requires candidates to work with customers on their projects either at our office or customer place. Candidate should have good communication skills, both verbal and oral. He/She should be a good team player.

Job Code: IMCVP2

Work Experience Requirements

• Minimum 2 to 4 years of industry experience
• Proficiency in Embedded C programming, verification approaches is must
• Good exposure to boot code flow, board/VP bring up
• Hands on experience of system debugging tools like Lauterbach /any other debug tools, software flow analysis, root cause of failure analysis
• Fundamental knowledge  of processor architecture, peripheral interface, different bus architecture
• Work exposure on verification coverage tools like code coverage, Quality Center, ReqPro is added advantage
• Exposure to mobile chipset/product will be added advantage with preference ARM cores
• Familiarity with Configuration management Systems, preferably Clearcase

Education Requirements: B.E/B.Tech or M.E/M. Tech in EE/CS from reputed institution

Please send your resume with job code in the subject line or contact us at following address:
Interra Systems
Kalyani Platina, No.24, Phase I, 2nd Floor, EPIP Zone, Whitefield,
Bangalore – 560066
Phone: +91 80 25130200
Fax: +91 80 25130220
Email: HRindia@interrasystems.com

General Description:

The individual will be responsible work as individual contributor and lead/guide the team on RTL co-verification of designs. The job requires candidates to work with customers on their projects either at our office or customer place. Candidate should have good communication skills, both verbal and oral. He/She should be a good team player.

Job Code: IMCVP3

Work Experience Requirements

• Minimum 4 to 5 years of industry experiencev
• Proficiency in Specman –e , VHDL , Verilog , C/C++, Perl is a must
• Familiarity with System C and participation in specman verification of a reference model written in C/C++/System C is needed
• Expertise in functional verification and debugging of ASIC / VLSI Designs using Specman-e verification language with a good exposure to EDA Verification tools from Mentor
• Expertise in development of BFMs, Testplan, Test cases and Vmanager Flow
• Hands on experience in developing and debugging Score boards , preferably with ARM processors, eVCs and dealing with c/c++ reference models
• Knowledge on code coverage and functional coverage analysis is essential
• Must have actively participated in a Complex SoC / IP Verification Team either at block level or top level using Specman

• Experience with Unix and Windows-XP development environments
• Familiarity with System Verilog will be an added advantage
• Familiarity with Configuration management Systems, preferably Clearcase
• Good understanding of Microprocessor, Microcontrollers, SoC architecture, bus protocols -particularly AMBA AHB, wireless baseband related peripherals, etc.

Education Requirements: B.E/B.Tech or M.E/M. Tech in EE/CS from reputed institution

Please send your resume with job code in the subject line or contact us at following address:
Interra Systems
Kalyani Platina, No.24, Phase I, 2nd Floor, EPIP Zone, Whitefield,
Bangalore – 560066
Phone: +91 80 25130200
Fax: +91 80 25130220
Email: HRindia@interrasystems.com

General Description:

Candidate should be a Computer Science/Electrical/Electronics graduate with prior experience of EDA flow development. He/She should have good understanding of design infrastructure software development. He/She should also be talented to propose, initiate new development in this area. He/She should will be working closely with cross functional and cross site teams. He/She should have the capability to understand and should comply with the organization’s best practices (quality/process) on the flow development.

Job Code: IMCEDA

Work Experience Requirements

Job Description:
EDA engineer to develop implementation methodology, flow automation and strategy for next generation CAD tools. This includes integration of implementation tools such as design compiler, ICC, primetime, Spyglass and testing, documentation of new methodologies. Developing specification, implementation, test and support of internal design flow and support software services.

This position requires below Programming / mandatory skills:

• OO Perl programming experience is must
• Basic XLM knowledge is must
• Overview knowledge of implementation tools
• Knowledge of version control systems (any one of clearcase, DesignSync, CVS etc.)
• Working (hands on) UNIX Shell Scripting Language

Desirable to have:

• TCl scripting exposure
• SoC design implementation (Synthesis, PnR, Equivalence check, Physical verification) is plus
• Knowledge of makefiles, Load sharing facility (LSF)
• Basic understanding in CMOS principles and basic chip design knowledge is plus

The candidate needs to be:

• Self motivated, analytical, flexible with good communication and ability to learn new areas, languages etc.
• Excellent written and verbal communication skills
• The candidate must be confident, self-sufficient, learn quickly, and have strong problem solving skills

Education Requirements: Bachelor/Master in Computer/Electrical/Electronics Engineering or equivalent from reputed institutional organizations

Please send your resume with job code in the subject line or contact us at following address:
Interra Systems
Kalyani Platina, No.24, Phase I, 2nd Floor, EPIP Zone, Whitefield,
Bangalore – 560066
Phone: +91 80 25130200
Fax: +91 80 25130220
Email: HRindia@interrasystems.com

General Description:

Candidate should be a Computer Science/Electronics/Electrical Engineering graduate with prior experience of software development in core Java. He/She should have good understanding of what it takes to develop well structured and easily maintainable software. He/She need to be highly proficient in Java Swing, GUI programming skills and ensure accuracy, completeness, and good coding style to ensure production quality development.

Job Code: IMCJV

Work Experience Requirements

This position is expected to be experienced (3-5 years) with the following mandatory skills/expertise:

• Good Programming skills: OO programming experience knowledge is must in Java
• Operating systems: Linux, Solaris, Window programming
• Good Programming skills: OO programming experience knowledge is must in Java
• Basic XML knowledge is must
• XML Schema is desired
• GUI programming experience desired
• Java swing preferred
• Basic UML knowledge (class diagrams) desired
• Experience with code generation useful

With the following desired/good to have Skills which is a plus:

• Makefiles knowledge
• Load sharing facility (LSF)

The candidate needs to be:

• Self motivated, analytical, flexible with good communication and ability to learn new areas, languages etc.
• Excellent written and verbal communication skills
• The candidate must be confident, self-sufficient, learn quickly, and have strong problem solving skills

Education Requirements: Bachelor/Master in Computer/Electrical/Electronics Engineering or equivalent from reputed institutional organizations

Please send your resume with job code in the subject line or contact us at following address:
Interra Systems
Kalyani Platina, No.24, Phase I, 2nd Floor, EPIP Zone, Whitefield,
Bangalore – 560066
Phone: +91 80 25130200
Fax: +91 80 25130220
Email: HRindia@interrasystems.com

General Description:

Candidate is expected to contribute individually by working hands-on layout design of SRAM/ROM/CAM/Custom memories and physical verification of memories. He/She is expected to mentor/lead team of memory layout designer depending on requirement of project. Candidate is required to interact and work with customer projects at their work place.

Candidate should have good communication skills, both verbal and oral. He/She should be a good team player.

Job Code: MLDX

Work Experience Requirements

• Candidate must have experience in layout design of memory leaf cells and at top level of memories
• He/She should have worked on 65nm/45nm/28nm process technologies and have understanding of issues like WPE, LOD effects
• He/She must have good understanding of physical verification checks – DRC, LVS, ERC and reliability checks – IR and EM
• He/She must have worked on cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks
• He/She must have good understanding of Basics of CMOS circuits
• Preferable candidate to have Skill and perl scripting experience to develop layout and schematic tiler
• He/She should have minimum of 2 – 7 years of experience

Education Requirements: Diploma in Electronics Or B.E / B.Tech in Electronics Engineering

Please send your resume with job code in the subject line or contact us at following address:
Interra Systems
Kalyani Platina, No.24, Phase I, 2nd Floor, EPIP Zone, Whitefield,
Bangalore – 560066
Phone: +91 80 25130200
Fax: +91 80 25130220
Email: HRindia@interrasystems.com

General Description:

Candidate is expected to work as individual contributor on characterization of memories for single port/dual port/register files/CAMs etc. Job require to develop test stimuli, spice decks, circuit simulation for timing and power, mis-match, margin simulations, bit cell analysis and debugging, and Monte Carlo simulations etc. Candidate must have good understanding in generating EDA views of memories. Candidate must have good experience in QA process for release of .libs and models.

Candidate is required to interact and work with customers on their projects either at our office or customer's work place.

Candidate should have good communication skills, both verbal and oral. He/She should be a good team player.

Job Code: MCHX

Work Experience Requirements

• Candidate must have transistor level circuit design experience of memories
• He/She should have worked on 65nm/45nm/28nm process technologies and must have understanding of design issues related to process.
• He/She must have good understanding of layout design of memories
• He/She must have worked on transistor level circuit simulation tools like Hspice/Hsim/Nanosim and characterization tools Altos/Magma to generate timing views and models
• He/She must have good understanding of circuit design concepts for low power CMOS circuits
• Preferable candidate to have understanding of front end memory models generation and validation
• He/She should have minimum of 2 – 7 years of experience
• Scripting experience in Perl is desirable

Education Requirements: B.E / B.Tech in Electronics Engineering

Please send your resume with job code in the subject line or contact us at following address:
Interra Systems
Kalyani Platina, No.24, Phase I, 2nd Floor, EPIP Zone, Whitefield,
Bangalore – 560066
Phone: +91 80 25130200
Fax: +91 80 25130220
Email: HRindia@interrasystems.com

General Description:

Candidate is expected to work individually or lead team of engineers on design of memories – single port/dual port/register files/CAMs etc. Job requires to do transistor level design to build low leakage and high performance memory compilers. He/She should have worked and understanding of bit cell analysis and full flow/methodology for compiler design. Candidate is expected to work with silicon validation team to debug design issues on silicon.

Candidate is required to interact and work with customers on their projects either at our office or customer’s work place.

Candidate should have good communication skills, both verbal and oral. He/She should be a good team player.

Job Code: MCDX

Work Experience Requirements

• Candidate must have transistor level circuit design experience of memories
• He/She should have worked on 65nm/45nm/28nm process technologies and must have understanding of design issues related to process
• He/She must have good understanding of layout design of memories, physical verification and reliability checks
• He/She must have worked on cadence tools for layout design and Cadence/Mento /Synopsys tools for circuit simulation
• He/She must have good understanding of circuit design concepts for low power CMOS circuits
• Preferable candidate to have understanding of front end memory models generation and validation
• He/She should have minimum of 2 – 7 years of experience

Education Requirements: B.E/B.Tech in Electronics Engineering

Please send your resume with job code in the subject line or contact us at following address:
Interra Systems
Kalyani Platina, No.24, Phase I, 2nd Floor, EPIP Zone, Whitefield,
Bangalore – 560066
Phone: +91 80 25130200
Fax: +91 80 25130220
Email: HRindia@interrasystems.com