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Cheetah - System Verilog Analyzer

Cheetah provides a customizable, robust, high performance, and easy to integrate System Verilog (IEEE 1800-2005) and Verilog (IEEE 1364-1995, 2001, 2005) parser and elaborator front-end for EDA tools.

Cheetah parses the complete language and creates an in-memory Object Model. Applications can then access the design information instantly, thus saving enormous time and resources. Rather than spending time writing parsers, designers can now spend time designing their solutions. In addition, Cheetah supports PSL (IEEE 1850) analysis for both embedded PSL and external verification units. Cheetah offers control options enabling applications to work with PSL and System Verilog together.

Key Features

• Full System Verilog support for IEEE 1800-2005
• Additional support for PSL 1850, V1.1 and V1.01
• Backward compatibility with IEEE 1364-2005, IEEE 1364-1995, OVI 2.0
• High performance System Verilog parsing and elaboration
• Industry standard library management mechanism
• Well-defined set of intuitive API to work with Object Model information
• Dynamic modification of the Object Model
• Optional RTL Subset semantics checks
• API functions for Expression Evaluation, Partial Elaboration, Partial analysis, and more
• Highly customizable: customized functions, error handlers, user-defined attributes, user-defined meta comments, and more