Jaguar - The VHDL Analyzer

Jaguar provides a robust, high performance, and easy to integrate VHDL parser and elaborator front-end for EDA tools. This industry compliant product parses the complete VHDL language (IEEE 1076) and creates an in-memory Object Model (OM). Applications can then access the design information instantly, thus saving enormous time and resources. Rather than spending time writing parsers, designers can now spend time designing their solutions. Jaguar also supports PSL (IEEE 1850) analysis for both embedded PSL and external verification units.

Jaguar is designed with the needs of EDA tool developers in mind. It can be used as the VHDL front-end for diverse set of EDA applications to increase the speed of development with a major reduction in cost.

Key Features

• Support both VHDL-87 and VHDL-93 language versions
• Additional support for PSL 1850, V1.1, and V1.01
• Language compliant library management for incremental compilation
• Capability to scan and sort based on analysis order
• Provides intuitive API to access Object Model information
• Dynamic modification of the Object Model
• Optionally performs RTL Subset semantic checks
• API functions for Expression Evaluation, Elaboration, Partial analysis, and more
• Highly customizable: customized functions, error handlers, user-defined attributes, user-defined meta comments, and more