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Most of the complex SoC designs today use one or more of Verilog, SystemVerilog and VHDL to implement various sub-systems. EDA tool developer needs to provide support for mixed language parsing.
MixedHDL from Interra Systems uses Cheetah, the Verilog and SystemVerilog front-end analyzer and Jaguar, the VHDL front-end analyzer to bring MixedHDL capability for EDA tool developers. Programming layer of MixedHDL analyzes mixed designs and elaborates cross-HDL instances. EDA tool developers can bring mixed-language support to their tool quickly. Language specific functionality is available through Cheetah and Jaguar API layer.
MixedHDL supports following EDA standards:
MixedHDL in conjunction with Cheetah and Jaguar parses all versions of standards of Verilog, SystemVerilog and VHDL and creates an in-memory Object Model. Applications can then access the design information instantly using efficient generic programming interface. Standard compliant and easy to use building blocks from Interra Systems enable users to reduce time-to-market by saving a significant amount of development time.
Front-end analyzers from Interra Systems are widely used by top-tier EDA tool developers as a universal front-end to their design solutions. Interra’s customers include top-tier EDA vendors, EDA startup companies and internal CAD groups of SoC companies. EDA Tools that integrate Interra’s EDA Objects are in production-use on thousands of chip designs.
Interra ensures its front-ends keep pace with language enhancements, capacity and quality requirements.