Addressing
the needs of ASIC/Soc professionals and EDA tool developers who need to
verify and simulate designs in mixed Verilog and VHDL, Interra offers
MVV, a mixed language Digital Design Elaborator. Targeted as a customizable
front-end for System Verilog and VHDL based mixed design applications
such as simulation and synthesis, MVV is compliant with industry standard
simulators and other tools. Available as library of "C" APIs,
MVV can be seamlessly integrated with "C" or "C++"
applications and used as a front-end to various EDA applications.
MVV analyzes mixed designs and elaborates cross-HDL instances. MVV is built over Interra's popular Verilog and VHDL analyzers: Cheetah and Jaguar. MVV users, therefore, have the dual advantage. They can use Cheetah and Jaguar APIs to analyze and modify designs, and use MVV APIs to verify cross-HDL binding of instances. Enabling the user to manage Verilog and VHDL libraries, optimize elaboration, and access information from elaborated masters, MVV's APIs are complete, function-rich, and intuitive.
