EDA Solutions


Interra Inside
  • Spyglass Rule Checker - Atrenta
  • N2C System Designer - CoWare
  • D-fabrix Reconfigurable Algorithm Processor - Panasonic
  • Vstation product family hardware emulator - Ikos/Mentor
  • Blast Fusion, a physical synthesis product - Magma
  • Formality, a Formal Verification system - Synopsys
  • TurboCheck, testability analysis - Syntest
  • eTools for Nextreme platform - eAsic
  • 0in Formal Verifier - Mentor
  • Hammer acceleration system - Eve
  • 360 Verifier - OneSpin Solutions
  • Xtreme and XCite systems - Cadence
  • SPEED Compiler - Carbon Design
  • Focus, design constraint generation - Fishtail
  • Spyglass Rule Checker - Atrenta
  • N2C System Designer - CoWare
  • D-fabrix Reconfigurable Algorithm Processor - Panasonic
  • Vstation product family hardware emulator - Ikos/Mentor
  • Blast Fusion, a physical synthesis product - Magma
  • Formality, a Formal Verification system - Synopsys
  • TurboCheck, testability analysis - Syntest
  • eTools for Nextreme platform - eAsic
  • 0in Formal Verifier - Mentor
  • Hammer acceleration system - Eve
  • 360 Verifier - OneSpin Solutions
  • Xtreme and XCite systems - Cadence
  • SPEED Compiler - Carbon Design
  • Focus, design constraint generation - Fishtail
  • Spyglass Rule Checker - Atrenta
  • N2C System Designer - CoWare
  • D-fabrix Reconfigurable Algorithm Processor - Panasonic
  • Vstation product family hardware emulator - Ikos/Mentor
  • Blast Fusion, a physical synthesis product - Magma
  • Formality, a Formal Verification system - Synopsys
  • TurboCheck, testability analysis - Syntest
  • eTools for Nextreme platform - eAsic
  • 0in Formal Verifier - Mentor
  • Hammer acceleration system - Eve
  • 360 Verifier - OneSpin Solutions
  • Xtreme and XCite systems - Cadence
  • SPEED Compiler - Carbon Design
  • Focus, design constraint generation - Fishtail
  • Spyglass Rule Checker - Atrenta
  • N2C System Designer - CoWare
  • D-fabrix Reconfigurable Algorithm Processor - Panasonic
  • Vstation product family hardware emulator - Ikos/Mentor
  • Blast Fusion, a physical synthesis product - Magma
  • Formality, a Formal Verification system - Synopsys
  • TurboCheck, testability analysis - Syntest
  • eTools for Nextreme platform - eAsic
  • 0in Formal Verifier - Mentor
  • Hammer acceleration system - Eve
  • 360 Verifier - OneSpin Solutions
  • Xtreme and XCite systems - Cadence
  • SPEED Compiler - Carbon Design
  • Focus, design constraint generation - Fishtail
  • Spyglass Rule Checker - Atrenta
  • N2C System Designer - CoWare
  • D-fabrix Reconfigurable Algorithm Processor - Panasonic
  • Vstation product family hardware emulator - Ikos/Mentor
  • Blast Fusion, a physical synthesis product - Magma
  • Formality, a Formal Verification system - Synopsys
  • TurboCheck, testability analysis - Syntest
  • eTools for Nextreme platform - eAsic
  • 0in Formal Verifier - Mentor
  • Hammer acceleration system - Eve
  • 360 Verifier - OneSpin Solutions
  • Xtreme and XCite systems - Cadence
  • SPEED Compiler - Carbon Design
  • Focus, design constraint generation - Fishtail
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Other Analyzers


Designed to meet the needs of EDA tool developers, Interra's suite of Standard Language Analyzers provide a memory optimal, robust, and easy-to-integrate front-end for standard languages and formats. Enabling EDA tool developers to concentrate on their core competency, rather than spending time writing parsers, these analyzers save resources and time to market high quality EDA products.

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Product Name Description
UPF Analyzer Supports Accellera standard UPF 1.0, can be easily integrated in TCL and C++ environment Download Datasheet
CPF Analyzer The object model can be easily accessed using the analyzer's C++ interface enabling seamless integration with C++ based EDA Tools. Download Datasheet
SDF Analyzer Supports SDF 2.0, 2.1, 3.0 and 4.0. Can be customized to store only typical, max, or min delays. Parses 18M lines of SDF in 2 minutes
SPEF Analyzer Supports IEEE 1481 standard. Effective object model handling of coupling capacitor, name map, and parasitic values (singlet vs triplet). Capable of handling SPEF that are more than 2 GB in size. Provides optional callback mechanism for handing application specific needs
DSPF/RSPF Analyzer Supports both DSPF and RSPF as per Cadence's SPF version 5.1. Effective object model handling of coupling capacitor, name map, and parasitic values. Provides optional callback mechanism for handing application specific needs
SLF (Liberty) Analzer Supports SLF 2007.03. The object model stores expressions as expression trees, hereby reducing post processing by the applications. Supports Scalable Polynomial Delay and Power Models Download Datasheet
VCD Analzer Supports VCD format as defined under IEEE 1364 standard. Provides optional callback mechanism for handling application specific needs
SAIF Analyzer Supports Synopsys SAIF, version 10.02. Provides optional callback mechanism for handing application specific needs
HSPICE Analyzer Fully supports HSPICE language version W-2004.09. Parses HSPICE configuration file to set search paths and other information automatically. Supports library management including parsing library files and expanding library calls. Recognizes and expands wildcards in output cards. Performs expression evaluation with support for calls to built-in and user defined functions Download Datasheet
GDSII Analyzer Fully supports GDSII version 3.0. Provides APIs to access the object model information, such as hierarchy, geometries, and pin information. Provides a comprehensive suite of utilities to save time and reduce development cycle. These utilities include Comparator, Flattener, Viewer, and GDSII-ASCII-GDSII Converter