Interra Systems develops, software components, which enable EDA tool developers and memory designers to create products rapidly at a lower cost. Products from Interra Systems are widely used by major SoC and Technology companies as well as start-ups.
MC2 - Memory Design Automation solution offers a memory design environment for standard and embedded memories. Leading edge designers who use memories either for standard memory design or embed memory, within their architectures, have long needed such an automated, error free, and scalable design environment. MC2 also provides a platform for seamless migration to new processes. By enhancing the overall methodology for the design and distribution of memories, MC2 ensures the reuse of a base design over many generations of sub-micron processes. Numerous users have taken advantage of MC2 capabilities for scaling their memory designs to higher densities, placing memories within their SoC, ASIC or IC designs, and making their design process more efficient.
EDA Objects product family and their associated services are widely used by EDA and design engineers as components of their design and CAD solutions. This standard compliant, easy to use product family enables users to reduce their cost while saving a significant amount of development time. EDA Objects are being used widely in a variety of tool development environments, making these objects the most robust front-end for EDA tools in the industry. Engineers who have incorporated EDA Objects in their solutions have seen savings of upto 30% in time-to-market. Use of Interra's test suites can provide additional quality and cost benefits.
| Product Name | Description |
|---|---|
| MC2, the Memory Development System | Memory Development System for standard and embedded memories. |
| Beacon, HDL/HVL Test Suites | Family of test suites for RTL-Verilog, RTL-VHDL, Verilog-2001, Mixed Verilog VHDL, System Verilog, System Verilog Assertions, and PSL |
| Concorde, fast Synthesis/ Elaborator | Fast RTL Synthesis/elaboration for System Verilog, Verilog, VHDL, and mixed designs. Quick synthesis can be used for verification, acceleration, and estimation purposes |
| Cheetah, the Verilog, SV Front-End | Complete language front-end for System Verilog applications. Provides access to the parse tree through APIs |
| Jaguar, the VHDL Front-End | Complete language front-end to VHDL applications. Provides access to the parse tree through APIs |
| NOM, Netlist Front-End | Language independent front-end for netlist applications supporting Verilog, VHDL, and EDIF 200 formats |
| Other Analyzers, EDA Standard Front-Ends | Analysis of other standard languages is also supported. Standards supported are: UPF, SDF, SPEF, DSPF/RSPF, SLF, HSPICE, SAIF, VCD, and GDSII. EDA applications can quickly access data defined in standard languages using APIs |
